1. Field of the Invention
The present invention relates to a semiconductor device in which a partially-depleted SOI MOSFET (Silicon On Insulator--Metal Oxide Semiconductor--Field-Effect Transistor) and fully-depleted SOI MOSFET are provided on the same substrate, and a method of fabricating such a semiconductor device. In greater detail, the invention relates to a semiconductor device, and to the fabrication method of the semiconductor device, in which the difference in threshold voltage between a fully-depleted SOI MOSFET and partially-depleted SOI MOSFET is small, and moreover, in which the impurity concentration of the channel region of the fully-depleted SOI MOSFET is higher than in the prior art.
2. Description of the Related Art
An SOI MOSFET formed on an SOI substrate having an SOI layer has the advantages of small junction capacitance of the source/drain regions and a small substrate bias effect compared with a MOSFET that is formed on a bulk substrate of the prior art. This type of SOI MOSFET is receiving attention as a device with excellent high-speed performance capabilities.
There are two types of SOI MOSFET: partially-depleted SOI MOSFET and fully-depleted SOI MOSFET. A fully-depleted SOI MOSFET is a MOSFET in which film thickness T.sub.SOI of the SOI layer is thinner than the maximum depletion layer width W.sub.max ; and a partially-depleted SOI MOSFET is a MOSFET in which the film thickness T.sub.SOI of the SOI layer is greater than the maximum depletion layer width W.sub.max. The maximum depletion layer width W.sub.max is given by the following equation: EQU W.sub.max =(2.epsilon..sub.si.epsilon..sub.0 2.phi..sub.F /qN.sub.A).sup.1/2+L EQU .phi..sub.F =(kT/q) ln(N.sub.A /n.sub.i) EQU =0.0259 ln(N.sub.A /1.5.times.10.sup.10) (1)
(when T=300K) where .epsilon..sub.si is the relative dielectric constant, .epsilon..sub.0 is the dielectric constant of a vacuum, q is the elementary charge, N.sub.A is the concentration of impurities, k is Boltzmann's constant, and T is temperature.
Because its threshold voltage can be set to a high level, a partially-depleted SOI MOSFET can suppress the standby leakage current of a transistor to a low level. A fully-depleted SOI MOSFET, on the other hand, can reduce subthreshold swing (S) and therefore enable high-speed operation at low voltage.
LSI with excellent characteristics are capable of high-speed operation with a low standby leak current and electrical or electronic equipment can be realized by forming these two types of MOSFET on the same SOI substrate and combining them by circuitry.
Formation of a partially-depleted SOI MOSFET, however, requires a design in which film thickness T.sub.SOI of the SOI layer is increased, or the concentration of impurities N.sub.A is raised and W.sub.max decreased in accordance with equation (1).
Formation of a fully-depleted SOI MOSFET, on the other hand, requires a design in which film thickness T.sub.SOI of the SOI layer is decreased, or the concentration of impurities N.sub.A is reduced and W.sub.max increased in accordance with equation (1).
According to M. J. Sherony et al. in "Minimization of Threshold Voltage Variation in SOI MOSFETs" (Proceedings, 1994 IEEE International SOI Conference pp. 131-132, October 1994), a region in which threshold voltage is not dependent on the film thickness of the SOI layer and which maintains a fixed value is a partially-depleted MOSFET, and a region in which threshold voltage decreases together with a decrease in the film thickness of the SOI layer is a fully-depleted MOSFET.
In the above-cited reference, moreover, an SOI layer film thickness of 59 nm and a channel region impurity concentration N.sub.A of 5.times.10.sup.17 cm.sup.-3 results in a partially-depleted SOI MOSFET, while an SOI layer film thickness of 59 nm and a channel region impurity concentration N.sub.A of 2.times.10.sup.17 cm.sup.-3 results in a fully-depleted SOI MOSFET.
Referring to FIG. 1A-FIG. 1D, explanation is next presented regarding a prior-art fabrication method of a semiconductor device in which a fully-depleted MOSFET and a partially-depleted MOSFET are formed on the same substrate. In this method, an n-channel partially-depleted SOI MOSFET and an n-channel fully-depleted SOI MOSFET are formed on the same substrate by changing the impurity concentration in the channel region.
Element isolation oxide film 4 is first formed on a SOI substrate composed of silicon substrate 1, buried oxide film 2, and SOI layer 3 as shown in FIG. 1A, thereby forming fully-depleted SOI MOSFET formation region 12 and partially-depleted SOI MOSFET formation region 14. The film thickness of SOI layer 3 after the formation of element isolation oxide film 4 is set to, for example, 63 nm.
Next, boron is injected as an impurity for threshold control in a first gate boron injection process. The dosage in the first gate boron injection is set to, for example, 2.times.10.sup.17 cm.sup.-3, a concentration that enables formation of a fully-depleted SOI MOSFET.
Next, mask composed of resist is formed by photolithography in fully-depleted SOI MOSFET formation region 12, as shown in FIG. 1B. Boron is then selectively injected as an impurity for threshold control in only partially-depleted SOI MOSFET formation region 14 in a second gate boron injection process.
The dosage in the second boron injection process is set to, for example, 5.times.10.sup.17 cm.sup.-3, a concentration that, combined with the dosage of the previous first gate boron injection process, allows formation of a partially-depleted SOI MOSFET.
As shown in FIG. 1C, the mask is next removed and gate oxide film 5 is formed at a prescribed film thickness of, for example, 8 nm in all regions of the SOI substrate. The film thickness of SOI layer 3 is hereupon reduced by the film formation of gate oxide film 5 to approximately 59 nm.
Finally, as shown in FIG. 1D, gate electrode 6 is formed, following which impurity is injected for source/drain region formation, and source/drain region 7 is formed.
The above-described fabrication method results in film thickness T.sub.SOI.sup.1 of SOI layer 3 of T.sub.SOI.sup.1 =59 nm and a channel region impurity concentration N.sub.A of 2.times.10.sup.17 cm.sup.-3 in fully-depleted SOI MOSFET formation region 12. In partially-depleted SOI MOSFET formation region 14, on the other hand, film thickness T.sub.SOI.sup.2 is 59 nm, and the channel region impurity concentration N.sub.A is 5.times.10.sup.17 cm.sup.-3.
However, the construction of partially-depleted SOI MOSFET formation region 14 and fully-depleted SOI MOSFET formation region 12 in the above-described method are distinguished only by the impurity concentrations, and this results in a large difference in threshold voltage V.sub.t between partially-depleted SOI MOSFET 14 and fully-depleted SOI MOSFET 12. This difference is, for example, 0.5 V in the example of the previously cited reference, and performance is therefore degraded. In addition, the impurity concentration of fully-depleted SOI MOSFET 12 must be made much lower, rendering the construction susceptible to the short channel effect.
On the other hand, forming both of partially-depleted SOI MOSFET 14 and fully-depleted SOI MOSFET 12 in their respective ideal constructions requires optimization of the film thickness of the SOI layer and the impurity concentration of each of partially-depleted SOI MOSFET 14 and fully-depleted SOI MOSFET 12, thereby leading to more processes as well as higher fabrication costs.